changing to a multiple frequency clock

One of my goals for this project was to push the computer’s clock speed, possibly overclocking it!

I plan to do this by replacing the current crystal oscillator with one with a significantly higher frequency. I will then feed this into a circuit that divides the frequency of the crystal oscillator into fractions, which can then be tapped at different points. I would then have multiple frequencies which I could test it at. I want to design the frequency divider circuit so that it has a range of values that include a known working frequency (1MHz) and higher, including some that definitely won’t work at the moment. This way I have stable frequencies to work with and frequencies that I can make adjustments to, to see if I can get the computer to work at. As well as making modifications to the hardware, there will need to be software modifications.

To keep with the remit of using era-appropriate parts, I will look to use 74 or 40 series ICs. There are a number of possibilities but I want to use a 4040, which is a 12-stage binary ripple counter. This IC contains 12 master-slave flip-flops. The output of each flip-flop feeds the next and the frequency of each output is half of the previous.

There is a reset pin but as I want this running all of the time, I have no plans to use it. RESET is active-high, so I will tie it to ground

The frequency of the crystal oscillator that I want to use is 20 MHz. The maximum frequency that WDC say that their 6502 can be used at is 14 MHz. This would only work if all of the other circuitry and software is also able to operate at that frequency as well. Even so, this gives me an upper theoretical to aim for. I wanted to go for a frequency above this so that I have plenty of room to explore overclocking. This will include frequencies close to what is currently working and also some that are high enough to experiment with.

As there are 12 stages in the 4040, I will use a switch with 12 selections, so I will use a 1-pole 12-selection rotary switch. 12 stages means that it will divide by a total of 256.

20 MHz
10 MHz
5 MHz
2.5 MHz
1.25 MHz
625 KHz
312.5 KHz
156.25 KHz
78.125 KHz
39.062.5 KHz